Supplier registry
22 listings — find a supplier by what they actually build.
Every company describes what it does in the same simple fields, so you can search and filter on real capabilities — protocol, methodology, coverage, lead time, foundry — and compare on facts instead of sales pitches.
22 of 22 shown
Aether Design made to order
org-aether
Design-led shop offering RTL plus a smoke-level UVM environment. We deliver working testbenches but do not commit to high function…
IP designDesign verificationAXI4AXI4 LiteAPB
lead 3–6w · cov 70–85% · Fixed price
ByteForge IP
org-byteforge
Catalog of configurable DMA and peripheral IP cores with AXI/APB interfaces. Licensing only.
IP licensingAXI4AXI4 LiteAPB
lead 1–2w · — · Royalty
Cortex Microsystems
org-cortex-micro
Licensable 32-bit RISC CPU core with AXI4 host interface. IP licensing only.
IP licensingAXI4AHB
lead 1–3w · — · Royalty
CoverPoint Labs made to order
org-coverpoint
Deep UVM verification with rigorous functional coverage modelling for complex SoC fabrics. Thorough but deliberate — we do not rus…
Design verificationAXI4AXI4 LiteAPBCHI
lead 10–16w · cov 97–100% · Fixed price
DeepCoverage made to order
org-deepcoverage
Specialists in AXI/ACE coherent fabric verification. UVM plus targeted formal for corner cases. We drive functional coverage to cl…
Design verificationAXI4ACEACE LiteCHI
lead 4–7w · cov 96–100% · Fixed price
FormalEdge made to order
org-formaledge
Formal-only verification house. We write SVA properties and run unbounded proofs with SymbiYosys and JasperGold. We do not build s…
Design verificationAXI4AXI4 LiteAPB
lead 3–6w · cov 100–100% · Fixed price
FPGAForge made to order
org-fpgaforge
We port SoC RTL to FPGA, build prototyping harnesses, and bring up boards. Prototyping, not block-level verification.
FPGA prototypingAXI4AXI4 LitePCIE
lead 3–8w · — · Time & materials
Helios Verification made to order
org-helios
UVM design-verification specialists for high-throughput interconnect and coherency. We build constrained-random UVM environments, …
Design verificationAXI4AXI3AXI4 LiteACEACE Lite
lead 4–7w · cov 95–100% · Fixed price
Meridian Memory
org-meridian-mem
Ultra-low-leakage single-port register file memory compiler on GlobalFoundries 22FDX. Deep-sleep data retention at minimal standby…
IP licensing
lead 1–3w · — · Royalty
MetricDV made to order
org-metricdv
Coverage-driven UVM verification with emulation for long soak tests on coherent fabrics. We commit to coverage closure and ship as…
Design verificationAXI4ACECHI
lead 5–8w · cov 95–100% · Fixed price
NanoBridge IP
org-nanobridge
Licensable, silicon-proven AXI4 interconnect IP with configurable masters/slaves. Comes with integration collateral. This is an IP…
IP licensingAXI4AXI4 LiteAPB
lead 1–2w · — · Royalty
OpenLane Collective made to order
org-openlane-collective
Python-first verification using cocotb. Great for fast bring-up and CI, but we do not build SystemVerilog UVM environments.
Design verificationAXI4AXI4 LiteWishboneAPB
lead 2–5w · cov 85–95% · Fixed price
PhysIQ made to order
org-physiq
Backend physical design: floorplanning, place-and-route, timing and DFT for advanced nodes. No front-end verification.
Physical designAXI4
lead 6–12w · — · Time & materials
QuantaVerify made to order
org-quantaverify
UVM verification for streaming and datapath blocks. Strong coverage methodology, but we deliver the testbench and coverage report …
Design verificationAXI4Axi StreamAXI4 Lite
lead 3–6w · cov 95–99% · Fixed price
RTLWorks made to order
org-rtlworks
We design synthesizable RTL for peripherals and interconnect from spec. Design only — verification is handled by your team or a pa…
IP designAXI4AXI4 LiteAPBAHB
lead 4–10w · — · Time & materials
SignalPath DV made to order
org-signalpath
Enterprise-grade UVM verification with directed and constrained-random suites, assertions and coverage closure. Large-team engagem…
Design verificationAXI4AXI4 LiteAPBACE
lead 4–7w · cov 96–100% · Fixed price
Silicon Sutra made to order
org-siliconsutra
Full-service RTL design and UVM verification for AXI-based subsystems. We can verify your existing interconnect RTL or design and …
IP designDesign verificationIP integrationAXI4AXI3AXI4 LiteAPBAHB
lead 5–8w · cov 90–98% · Fixed price
TrueNorth Verification made to order
org-truenorth
Premium UVM + formal sign-off for coherent interconnect and cache. Fast turnaround, high confidence, priced accordingly. Assertion…
Design verificationAXI4ACEACE LiteCHI
lead 2–5w · cov 98–100% · Fixed price
Veridian Labs made to order
org-veridian
Interconnect-focused UVM verification with functional coverage closure and SVA. We verify existing AXI4 fabric RTL and deliver a f…
Design verificationAXI4AXI4 LiteAXI3
lead 4–8w · cov 92–99% · Fixed price
Verifyon made to order
org-verifyon
UVM verification for low-speed peripherals and control buses. APB/AHB focus; we do not take on high-performance AXI coherency work…
Design verificationAPBAHBAHB LiteSPII2C
lead 2–5w · cov 95–100% · Fixed price
VeriSphere made to order
org-verisphere
Generalist UVM verification across AXI, AHB and APB subsystems. We deliver a complete UVM environment with assertions and coverage…
Design verificationAXI4AXI4 LiteAPBAHBAHB Lite
lead 3–6w · cov 93–99% · Fixed price
VoskenAI made to order
org-voskenai
End-to-end automated silicon IP design and verification. From a plain-English brief we generate synthesizable SystemVerilog (Veril…
IP designDesign verificationIP integrationAXI4AXI3AXI4 LiteAxi StreamACE Lite
lead 1–6w · cov 90–100% · Per block